DSP Software Engineer
Pretoria East
Minimum Requirements:
Synchronous Digital Design Principles. VHDL or Verilog development for FPGAs FPGA timing analysis and timing HDL toolchains Generating VHDL from MATLAB toolchain Experience in developing embedded applications with
firmware development, VHDL Quartus and the ModelSim toolchain. Responsibilities: Develop digital communication
development, VHDL and Modelsim toolchain will be beneficial. Responsibilities: Development of embedded